Variable pattern pulse generator



J. D. BAGLEY July 20, 1965 VARIABLE PATTERN PULSE GENERATOR Filed Nov.10, 1961 FIG.1

DELAY 24 BISTABLE FLIP- FLOP AND CLOCK PULSE GENERATOR FIG. 2

CLOCK OUTPUT CLOCK 2 3 4 s s s s OUTPUT INVENTOR JOHN D. BAGLEY ATTORNEYUnited States Patent 3,196,353 VARIABLE PATTERN PULSE GENERATQR John D.Bagley, Ann Arbor, Mich, assignor to international Business MachinesCorporation, New York, N.Y., a corporation of New York 7 Filed Nov. 16,196i, Ser. No. 151,549 6 Claims. (ill. 328-55) This invention relates topattern generators and more particularly to a gated pulse generator forproviding a desired pattern of N pulses for each cycle of (N+M) possiblepulses from the generator.

In a system having a given clock pulse generator, where a differentpattern of pulses is required, it has been the practice to gate desiredones of the pulses from the generator by use of a gating circuit foreach pulse of the generator desired, in some instances inserting acommercially available ring counter having desired ones of the outputsfom the difierent stages gated while in other instances providing abinary counter in combination with a decoding circuit. Each of thesetechniques is not only costly, in a pecuniary sense, but in terms ofcomponents which increases the probability of operating failure.

It has been found that by constructing a circuit according to thisinvention the above disadvantages are overcome. If a simple clock pulsegenerator is provided which emits a pulse each increment or" time (twith each pulse having a predetermined pulse period duration k(t where(0 k l), means are provided for gating the pulses from the generator toprovide a number of N pulses for each cycle of (N +M possible pulsesfrom the generator. More specifically, the pulses from the generator arefed to a gating circuit. An output of the gating circuit is connectedback to a conditioning input of the gating circuit through a delayfeedback loop circuit. The feedback loop circuit comprises a bistableflip-flop switching device having a set input, a reset input, and anoutput taken oh the reset side of the device. A first delay device isconnected to the reset input of the flip-flop which acts to delay aninput thereto a predetermined multiple of k(t pulse periods. A seconddelay device is connected to the reset output of the flip-flop whichalso acts to delay an input thereto a predetermined multiple of k(tpulse periods. Whether the multiple of pulse periods k(t provided byeach of the AA and AB delay devices is an integral number and whetherthe integral number is even or odd is defined by and dependent upon thevalue of k. Both the set input of the flip-flop and the first delaydevice are connected to the output of the gating circuit while thesecond delay device is connected to the conditioning input of the gatingcircuit. For a desired output pulse pattern within a predetermined cycle(N +M the delay periods in a first embodiment for both the first andsecond delay devices are adjusted such that the total delay provided byboth delay devices and the associated flip-flop circui and AND gate is(N+M-1+2k)r and in a second embodiment both delay devices with theassociated circuitry are adjusted to provide a total delay of (N+Ml+k)z' Accordingly, it is a prime object of this invention to providean improved pulse pattern generator.

Another object of this invention is to provide a simple, yet improvedpulse pattern generator which is relatively cheap to construct.

Still another object of this invention is to provide a u gating circuitin combination with a clock pulse gen- 3,l%,358 Patented July 20, 1965ice The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of preferred embodiments of the invention, as illustrated inthe accompanying drawings:

in the drawings:

FIG. 1 is a circuit schematic according to this invention.

FIG. 2 is a representation of pulses applied to and pulses provided bythe circuit of FIG. 1 according to one embodiment of this invention.

FIG. 3 is a representation of pulses applied to, and the pulses providedby the circuit of FIG. 1 according to another embodiment of thisinvention.

Referring to the FIGS. 1 and 2, a circuit is shown which is capable ofproviding a desired output pulse pattern by selectively gating pulsesfrom a clock pulse generator 10. The generator llfi is adapted toprovide a pulse for each increment of time (t with each pulse having apulse duration or duty factor period of km). The duty factor k isdefined by the clock pulse width divided by the clock period (tTherefore, the duty factor k is k l). in order to simplify theconstruction and understanding of the circuit of FIG. 1, a duty factor,k of /2) will hereafter be employed and thus the pulse duration periodprovided by generator 10 is (t /2), as is shown in the FIG. 2 by asequence of pulses labelled clock having time designations t through IThe generator 10 is connected to an AND circuit 12. The AND circuit 12is provided with a conditioning input line 14 and an output line 16connected to a terminal 18. A bistable flip-flop switching device 20,such as a bistable Eccles-Jordan trigger, is provided having a set inputline 22 and a reset input line 24. The flip-flop is provided with areset output 26 and the flip-flop Zll operates to provide a high leveloutput voltage on the output line 26 when triggered to a stable resetcondition and a low level voltage on the output line 26 when triggeredto the set condition. A first delay device, AA, is connected to thereset input 24 of flip-flop 20. A second delay device, AB, is connectedto the reset output line 26 of flip-flop 26. The terminal 18 isconnected to an output line 23, the AA delay device and the set inputline 22 of flip-flop 20, while the AB delay device is connected to theconditioning input line 14 of AND circuit 12.

In operation, the flip-flop 20 is initially assumed to be in a resetcondition. Since the flip-flop 20 is in a reset condition, the initialpulse from generator 10 which is applied to the AND circuit 12 isconditioned by the input line 14 and passed to the output line 16 andthence to the output 28. This initial pulse from generator 10 is alsoapplied to the set input line 22 of flip-flop 20 to switch the flip-flopto the setcondition. The flip-flop 20 in switching to the set stablestate provides a low level voltage on the output line 26. This low leveloutput voltage is thereafter applied to input line 14 delayed by aperiod determined by the AB delay device. This low voltage condition online 14 cuts off any further output through the AND circuit 12. Thefirst pulse from generator it} is also applied, via output line 16 ofAND circuit 12 to the AA delay device. The AA delay device, at some timelater, applies a pulse to the reset input line 24 of the flip-flop 20causing the flip-flop 20 to switch to the reset stable state. Theflip-flop 20 in switching to the reset stable state provides a highlevel voltage output to the conditioning input line 14 delayed by a timeperiod determined by the AB delay device to thereby allow any succeedingpulse from the generator 10 to pass through AND circuit 12 and output 28thus starting the cycle over again.

Assume that it is desired to provide a particular number of N pulses atthe output 28 of circuit of FIG. 1 for each cycle of (N-I-M) possiblepulses from the source in FIG. 2 labelled output.

3 10. In the general case, where the pulse period is k(t and (0 k /2 thedelay provided by AA and AB is obtained by a general relationship:

(N+N1+2k)t -(AA+AB)(N+M)t where '(N1+k)l AB'(Nk)t0 When M N, and (O k1), a general relationship:

I exists, where As stated above, in order to simplify construction andan understanding of this pattern generator, a half pulse period of (t/2) will be employed. More specifically, assume it is desired to provideone pulse for every three pulses from the source 10 as is shown by apulse pattern The circuit of FIG. 1 is then constructed such that AA andAB provide a delay equal to a multiple of the half pulse period (t 2),where the multiple for both AA and AB delay devices is an odd integralnumber.

Since one pulse, N, is desired for every three possible pulses fromsource 10, and a pulse period of (t /2) is to be employed, then (0 k=/z) and (O k l) where M N allowing use of either one of the two generalrelationships given above. The delay periods AA and AB are then obtainedby use of either the first relationship, where k=' /2, which is givenby:

or the second relationship:

Thus, the AA delay device is constructed to have a delay period of (Zt-I-t /Z) while the AB delay device I is constructed to have a delayperiod of (t /2). Operation. of the circuit of FIG. 1 with the delaydevices AA and AB constructed as set forth above commences as is shownin the FIG. 2. At time t t a first pulse from the source 10 is initiallypassed through the AND circuit 12 to the output 28 which immediatelysets flip-flop 20 to provide a low voltage output on reset output line26 to the AB delay. device. The low voltage output con- 7 dition on line26 is delayed by the AB delay device (t /2).

Assuming the action of flip-flop 20 is instantaneous, the low voltageoutput condition is passed to the conditioning input line 14 at a time tthus inhibiting the passage. of any further pulses from source 10through AND circuit 12. The. first pulse from the clock source 10 isdelayed by the AA delay device until a time t at which time the resetinput 24 of flip-flop 20 is energized to reset the flip-flop 20 andprovide a high voltage output on line 26', The output of flip-flop 20 online 26 is applied to the AB delay device, fora period (t /2), andthence applied to the conditioning input 14 of AND circuit 12 at a timet allowing the next pulse at r 4 from source 14) to pass through'thegate 12 to the output 28.

Employing the alternate relationship as described above, the AB delaydevice is constructed so that AB=t and With the delay devices AA and ABconstructed to provide' the delays set forth above, again the firstpulse,

t -t from source 10 is passed through the AND circuit 12 to the output16 and thence to the output 28 of the circuit ofFIG. 1, which setsflip-flop 20 turning off the high level voltage signal to the AB delaydevice. The conditioning input 14 is then in the low level voltagecondition at t inhibiting the passage of any further pulses from source10 through AND circuit 12. The r 4 pulse from source 19 is' also appliedto the AA delay device and is applied to the reset input 24 of flipfiop20 at a time t providing a high voltage output signal on line 26 offlip-fiop 20 at this time. The high voltage signal on line 26 is thenapplied to the AB delay device and allowed to pass to the conditioninginput line 14 of AND circuit 12 at a time I Since there is no pulse fromsource lit at time t the circuit remains with a high voltage signal online 14 of AND circuit 12 allowing the next pulse, 1 4 from source 10 topass to V the output 28 of the circuit of FIG. 1.

A'Inore complicated pulse pattern of the type shown in the FIG. 3 issimply achieved by utilizing the above relationships for construction ofthe delay devices AA and AB. For instance, it may be seen that for everyfive pulses from the source 10, two pulses at the output 28 are to bedelivered, thus two pulses are to be gated on,

while three pulses are to be gated olf. According to the firstrelationship,

and 7 AB: t +t 2 With the devices AA and AB constructed to provide thedelay as set forth above, the circuit of FIG. 1 operates as follows:assuming the flip-flop 20 is initially in the reset condition, at I, afirst pulse is applied from source 10 and passed through AND gate 12 tooutput 28, delay device AA and the set input 22 of flip-flop 20. At thetime t the flip-flop 20 is switched to the set state turning olf thehigh voltage output to line 26. Since the output on line 26 is delayedby the AB delay device (t -I-t /Z), the conditioning input line 14 ofAND circuit 12 is still energized at the time t3 when the next pulsefrom source 10 is applied to the AND circuit 12. The second pulse, I -L,is passed through the AND circuit to the output 16. At time t, theconditioning input line 14 of AND circuit 12 is at a low voltage levelinhibiting any further pulses from source 10 to pass to the output 16 ofthe AND circuit. The first pulse from source 10 at t is also applied'tothe AA delay device and this pulse is delayed for a period (3t |t /2)and applied to the reset input of The flip-flop 20 is then switched tothe resetstable state to provide a high voltage output on line 26 to theAB delay device. The high voltage output on line 26 is thereafterapplied to the conditioning input line 14. after passing through the ABdelay device (t +t /2) time increments later. The conditioning inputline 14 is then at a high voltage level at t allowing the pulse t t'from source 10 to pass through AND circuit 12. The next pulse passedthrough the AND circuit 12 at 1' is applied to the reset input 24 offlip-flop 20' after passing through the AA delay device. This pulseappears at a time however, since the flip-flop 20 is already in thereset stable state, no change occurs in its operation. 7 Thus, the pulsefrom source 10 at a time t is allowed to pass to the output 28 as is thenext pulse ie- 14- The circuit of FIG. 1 can be constructed such thatthe AA and AB delay devices provide a delay as in accordance with thesecond method set forth above, in that:

With the AA and AB delay devices constructed to provide a delay periodas set forth above, the first pulse t t in FIG. 3, appearing at time tis passed through the AND circuit 12 since the flip-flop 20 is assumedto be in the normal reset condition. The pulse t t is then passedthrough the AND circuit 12 to the output 28; AA delay device; and setinput 22 of flip-flop 20. The flip-flop 20 is then switched to the setstable state turning off the high voltage output on line 26. The nextinput pulse t t from source appears at the AND circuit 12 at timedelayed from the initial input pulse for a period (t Since the delaydevice AB is constructed to provide a delay of 2.0: the conditioninginput 14 of AND circuit 12 is still up and the next pulse from source 10at time 1 also passes to the output 28 of the circuit delay device AAand the set input 22 of tlip flop 20. The initial pulse t t from source10 at time t; is applied to the reset input 24 of flip-flop delayed by atime (2t -l-t /2) due to the delay provided by AA delay device. Theflip-flop 20 is then switched to the reset stable state at i providing ahigh voltage output on line 26 to the AB delay device. The output online 26 is then passed through to the conditioning input 14 of ANDcircuit 12 delayed by a time (2.011,) provided by the AB delay device.Thus, the flip flop 20 is switched to the reset stable state at a time tand a voltage level is applied to the conditioning input 14 at I Theconditioning input 14 of AND circuit 12 remains at a high voltage levelwhen a pulse i -r from source 10 is applied thereto. The pulse i -t isthen passed through the AND circuit 12 to the output 28 of the circuit.The pulse i 4 passed to the output 28 is applied to the reset input 24of flip-flop 20 at a time 2 Since the flip-flop 20 is already in thereset stable state, this pulse has no effect. The pulse passed throughthe AND circuit 12 is applied to the AA delay device and the set input22 of flip-flop 20, switching the flip-flop 20 to the set stable state.The next pulse I -1 from source 10 is passed through the AND circuit 12since AB delay device provides a delay of (2.01 insuring that theconditioning input line 14 of AND circuit 12 is still up allowing thepassage of this pulse from source 10.

It should be noted that in the circuit explanation, the small delaywhich is introduced by the logical circuitry has not been considered andwhen constructing the circuit, this delay is compensated by a slightadjustment of AA and AB. Further, long patterns of practically anydesired complexity may be generated by chaining a number of individualpattern generators of the type described in FIG. 1. If each generator inthe chain feeds only generators with shorter cycles (Nl-M), thesynthesis task is made simple although this by no means assures aminimum component count.

In both embodiments of this invention described above, the minimummultiple of pulse periods k(t is seen to be an odd numbered integer,however this is only true where k is a fraction whose denominator is aneven number and the value of the fraction is k /z. If, on the otherhand, k is a fraction whose denominator is an odd number and the valueof the fraction is k /z, then the minimum multiple of pulse periods k(tprovided by each of the AA and AB delay devices is an even numberedinteger. In the case where k the multiple of pulse periods k(r providedby each delay device AA and AB then takes on a fractional order.

While the invention has been particularly shown and described withreference to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formand details may be made therein without departing from the spirit andscope of the invention.

What is claimed is:

1. A circuit for providing a desired number of N pulses within a cycleperiod of (Nl-M') possible pulses from a pulse generator adapted toprovide a series of pulses displaced by a time increment (t having apulse period duration of km), where (0 k 1); means comprising an ANDcircuit having a primary input, a conditioning input and an output and aconditioning circuit connected in feedback loop arrangement from theoutput of said AND circuit to the conditioning input of said AND circuitfor gating the pulses from said generator to provide a predeterminednumber of N pulses in each cycle of (N +M possible pulses from saidgenerator to the output of said AND circuit; said conditioning circuitcomprising; a bistable switching circuit having a set input, a resetinput, and a reset output; a AA delay device having an input and output,its output being connected to the reset input of said switching devicefor delaying an input thereto a first predetermined multiple of k(tpulse periods; a AB delay device having an input and output, its outputbeing connected to the reset output of said switching device fordelaying an output from said switching device a second predeterminedmultiple of k(t pulse periods, said first and second predeterminedmultiple of k(t pulse periods being determined by and dependent upon thevalue of k; means connecting the output of said AND circuit to the setinput of said switching device and the input of the AA delay device andmeans connecting the output of the AB delay device to the conditioninginput of said AND circuit.

2. The circuit as set forth in claim 1 wherein the cycle (N +M ofpossible pulses from said generator provided to the output of said ANDcircuit is related to both said AA and AB delay devices by arelationship 3. The circuit as set forth in claim 1, where the cycle (N+M) of possible pulses from said generator provided at the output ofsaid AND circuit is related to both said AA and AB delay devices by arelationship (N-1-M l +k)t AA+AB (N-1M)t where (N 1 +k) t AB N t 4. Thecircuit as set forth in claim 3, wherein said first and secondpredetermined multiples of k(t pulse periods are each odd numberedintegers.

5. The circuit as set forth in claim 3, wherein said first and secondpredetermined multiples of k(t pulse periods are each even numberedintegers.

6. A pattern generating circuit for producing a recurrent pulse patternhaving a predetermined number of pulses and blank positions whichcomprises:

a clock pulse generator;

an AND circuit having a primary input connected to the output of saidgenerator, a conditioning input and an output;

the combination of a bistable flip-flop circuit having first and secondconditioning inputs and a second condition output, the output of the ANDcircuit being connected directly to the first conditioning input of saidflip-flop and a first delay circuit connected between the output of saidAND circuit and the second conditioning input of said flip-flop 7 a a aa a a c and the generating circuit output terminal connected ReierencesQited by the Examiner directly to thfi outnut Of said AND CiI'CUit; t

a second delay circuit connected between the second 2 2 i I conditionoutput of'said flip-flop and the condition- ,89 16/59 Eckert et inginput of said AND circuit; 5

wherein said pattern generating circuit is initially set ARTHUR GAUSSPrimary Examme" to the second condition of said flip-flop upon the be-JOHN W. HUCKERT, Examiner. ginning of a pattern generating sequence.

1. A CIRCUIT FOR PROVIDING A DESIRED NUMBER OF N PULSES WITHIN A CYCLEPERIOD OF (N+M) POSSIBLE PULSES FROM A PULSE GENERATOR ADAPTED TOPROVIDE A SERIES OF PULSES DISPLACED BY A TIME INCREMENT (TO) HAVING APULSE PERIOD DURATION OF K(TO); WHERE (O<K<1), MEANS COMPRISING AN ANDCIRCUIT HAVING A PRIMARY INPUT, A CONDITIONING INPUT AND OUTPUT AND ACONDITIONING CIRCUIT CONNECTED IN FEEDBACK LOOP ARRANGEMENT FROM THEOUTPUT OF SAID AND CIRCUIT TO THE CONDITIONING INPUT OF SAID AND CIRCUITFOR GATING THE PULSES FROM SAID GENERATOR TO PROVIDE A PREDETERMINEDNUMBER OF N PULSES IN EACH CYCLE OF (N+M) POSSIBLE PULSES FROM SAIDGENERATOR TO THE OUTPUT OF SID AND CIRCUIT; SAID CONDITIONING CIRCUITCOMPRISING; A BISTABLE SWITCHING CIRCUIT HAVING A SET INPUT, A RESETINPUT, AND A RESET OUTPUT; A $A DELAY DEVICE HAVING AN INPUT AND OUTPUT,ITS OUTPUT BEING CONNECTED TO THE RESET INPUT OF SAID SWITCHING DEVICEFOR DELAYING AN INPUT THERETO A FIRST PREDETERMINED MULTIPLE OF K(TO)PULSE